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dsPIC33CK support for advanced instructions?

 
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laser_scientis



Joined: 12 Apr 2025
Posts: 1

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dsPIC33CK support for advanced instructions?
PostPosted: Tue Jul 08, 2025 11:45 am     Reply with quote
Hello. I am using the 5.115 compiler with a dsPIC33CK64MC105. I need to optimize various math processing routines, so I drop into assembly for that. I wanted to take advantage of the fast division instructions that are implemented on this chip, but apparently, the compiler doesn't support these. For example, this is the normal code produced by the compiler for a 16 bit / 16 bit signed division operation:
Code:
    # mc = ma / mb
    MOV ma,W4
    MOV mb,W3
    REPEAT  #11
    DIV.S  W4,W3
    MOV W0,mc

which requires 18 cycles for the division, as per the datasheet. This code works fine if I include it as an assembly block.
There is a DIV2 instruction group (DIV2.S, DIV2.U) which is supposed to complete in only 6 cycles, but if I try to introduce that instruction:
Code:
    // mc = ma / mb
    MOV ma,W4
    MOV mb,W3
    REPEAT  #5
    DIV2.S  W4,W3
    MOV W0,mc

the compiler gives an error Error#95 Expecting an opcode mnemonic DIV2:
There are other instructions that appear in the datasheet, such as DIVF and DIV2F (fractional divide) that are also flagged by the compiler as nonexistent.
Am I missing something, or is there any way of working around this?
Thanks for any advice.
Ttelmah



Joined: 11 Mar 2010
Posts: 19892

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PostPosted: Wed Jul 09, 2025 12:44 am     Reply with quote
Big answer here is talk to CCS.

You can bodge round a non existent instruction, by manually placing the
required bytes in the assembler. Years ago, there was a single instruction
and I generated macros to produce the correct bytes, with variables coded
into the bytes as well, but it is a lot of work, and I'd expect CCS to offer
a better workaround, or even add the instructions for you. They may well
already exist, but need sneaky coding.
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