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bschriek
Joined: 18 Dec 2007
Posts: 80
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| "getenv" doesn't know all the CLC register names |
 Posted: Fri Oct 18, 2024 2:49 am |
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PCW Compiler IED, PCB, PCM 5.118
This problem is already posted before!
Just another example....
| Code: | #include <16F18124.H>
#Fuses RSTOSC_HFINTRC_32MHZ,NOEXTOSC,NOCLKOUT,NOCKS,NOFCMEN,NOMCLR,LPBOR,BROWNOUT,BORV28,NOZCDDIS,NOPPS1WAY,NOSTVREN,NODEBUG,NOWDT
#Fuses NOBOOTBLOCK,NOSAF,NOWRT,NOWRTB,NOWRTC,NOWRTD,NOWRTSAF,NOLVP,PROTECT,PUT_64MS
#Device ADC=10 //MCLR is I/O
#use delay(clock= 32000000)
int16 i = 0;
int8 j = 0;
#bit TMR0IF = getenv("BIT:TMR0IF")
#bit TMR1IF = getenv("BIT:TMR1IF")
#bit NCO1IF = getenv("BIT:NCO1IF")
// Code underneath is accepted by compiler.
#byte CLCnCON =getenv("SFR:CLCnCON")
#byte CLCnGLS0=getenv("SFR:CLCnGLS0")
#byte CLCnGLS1=getenv("SFR:CLCnGLS1")
#byte CLCnGLS2=getenv("SFR:CLCnGLS2")
#byte CLCnGLS3=getenv("SFR:CLCnGLS3")
#byte CLCnPOL =getenv("SFR:CLCnPOL")
#byte CLCnSEL0=getenv("SFR:CLCnSEL0")
#byte CLCnSEL1=getenv("SFR:CLCnSEL1")
#byte CLCnSEL2=getenv("SFR:CLCnSEL2")
#byte CLCnSEL3=getenv("SFR:CLCnSEL3")
//
// Code underneath is NOT accepted by compiler anymore.
#byte CLC2CON =getenv("SFR:CLC2CON")
#byte CLC2GLS0=getenv("SFR:CLC2GLS0")
#byte CLC2GLS1=getenv("SFR:CLC2GLS1")
#byte CLC2GLS2=getenv("SFR:CLC2GLS2")
#byte CLC2GLS3=getenv("SFR:CLC2GLS3")
#byte CLC2POL =getenv("SFR:CLC2POL")
#byte CLC2SEL0=getenv("SFR:CLC2SEL0")
#byte CLC2SEL1=getenv("SFR:CLC2SEL1")
#byte CLC2SEL2=getenv("SFR:CLC2SEL2")
#byte CLC2SEL3=getenv("SFR:CLC2SEL3")
void main()
{
setup_adc(ADC_CLOCK_DIV_16); // Tad = 184µSec
setup_vref(VREF_OFF|VREF_ADC_OFF|VREF_COMP_DAC_OFF|TEMPERATURE_INDICATOR_DISABLED);
setup_DAC(DAC_OFF);
setup_timer_0(T0_INTERNAL|T0_DIV_1); // 32.000.000/4 = 8.000.000KHz t=0.125µsec x 65536 = 8,192mSec tot overloop.
setup_timer_1(T1_EXTERNAL|T1_DIV_BY_1); // External clock, T1CKI input
setup_timer_2(T2_DIV_BY_16 | T2_CLK_INTERNAL, 255, 1); // 32.000.000/4/16/256= 1952Hz Tp=512mSec. bereik is 0 tot 1023d.
setup_comparator(NC_NC_NC_NC);
setup_zcd(ZCD_DISABLE);
//
////////////// Undefined identifiers //////////////////
/*
CLC2CON = 0x82; // LC2EN enabled; INTN disabled; INTP disabled; MODE AND-OR;
CLC2GLS0 = 0x02; // LC2G1D3N disabled; LC2G1D2N disabled; LC2G1D4N disabled; LC2G1D1T enabled; LC2G1D3T disabled; LC2G1D2T disabled; LC2G1D4T disabled; LC2G1D1N disabled;
CLC2GLS1 = 0x02; // LC2G2D2N disabled; LC2G2D1N disabled; LC2G2D4N disabled; LC2G2D3N disabled; LC2G2D2T disabled; LC2G2D1T enabled; LC2G2D4T disabled; LC2G2D3T disabled;
CLC2GLS2 = 0x02; // LC2G3D1N disabled; LC2G3D2N disabled; LC2G3D3N disabled; LC2G3D4N disabled; LC2G3D1T enabled; LC2G3D2T disabled; LC2G3D3T disabled; LC2G3D4T disabled;
CLC2GLS3 = 0x02; // LC2G4D1N disabled; LC2G4D2N disabled; LC2G4D3N disabled; LC2G4D4N disabled; LC2G4D1T enabled; LC2G4D2T disabled; LC2G4D3T disabled; LC2G4D4T disabled;
CLC2POL = 0x00; // LC2G1POL not_inverted; LC2G2POL not_inverted; LC2G3POL not_inverted; LC2G4POL not_inverted; LC2POL not_inverted;
CLC2SEL0 = 0x19; // LC2D1S PWM7_OUT;
CLC2SEL1 = 0x19; // LC2D2S PWM7_OUT;
CLC2SEL2 = 0x19; // LC2D3S PWM7_OUT;
CLC2SEL3 = 0x19; // LC2D4S PWM7_OUT;
*/
while(true)
{
delay_ms(100);
}
} |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19538
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| Posted: Fri Oct 18, 2024 3:20 am |
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So, tell CCS.
That way they'll update these on the next release. Posting this here is
rather pointless. |
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bschriek
Joined: 18 Dec 2007
Posts: 80
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| Posted: Fri Oct 18, 2024 4:31 am |
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| Yes, I all ready did. |
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temtronic
Joined: 01 Jul 2010
Posts: 9243
Location: Greensville,Ontario
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| Posted: Fri Oct 18, 2024 5:31 am |
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I wouldn't expect CCS to fix this 'overnight'. Their compilers have 1,000s of PICs to deal with,100s of 'bugs' and a handful of programmers.
It takes TIME to open up a bug report, properly test and confirm,decide on a 'fix',recode, retest, confirm 'fix' DID fix the original bug AND not introduce a new 'bug'.
I can see a lot of time to do this.Hmm, is your reported bug JUST for the PIC you use or is it in the family or worse case, common to all PICS ? If 'in the family', that could mean 20-100 more PICs that need to be updated and tested. |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19538
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| Posted: Fri Oct 18, 2024 6:07 am |
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I think it'd be 'next release'. Like the binary database of chip features, I expect
this is actually a database that is compressed and built inside the compiler. |
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bschriek
Joined: 18 Dec 2007
Posts: 80
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| Posted: Fri Oct 18, 2024 6:42 am |
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| It seems the 16F17114, 16F18114, 16F17124 and 16F18124 have the same problem. |
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waffles
Joined: 21 Dec 2021
Posts: 10
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| Posted: Tue Oct 22, 2024 2:14 pm |
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After looking at the datasheet for the 16F18124 I'm not sure what the issue is?
It doesn't have distinct registers for each module - you select what CLC you want to configure via the CLCSELECT register. |
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bschriek
Joined: 18 Dec 2007
Posts: 80
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| Posted: Wed Oct 23, 2024 12:39 am |
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Underneath the comment of Richard (CCS Support).
Clear description and I will try it asap, Thanks!
For whichever chip your using there will be the following built-in
> functions for the CLC peripheral:
>
> setup_clcX()
> clcX_setup_input()
> clcX_setup_gate()
>
> X being the CLC peripheral you want to setup, for a device with 4 CLC
> peripherals it can be 1..4. The following is an example showing how
> to setup CLC1 in OR XOR mode so that it will do an XOR of the inputs
> on CLCIN0 and CLCIN1 pins:
>
> //Initialize the CLC1 peripheral in or-xor mode
> setup_clc1(CLC_ENABLED | CLC_MODE_OR_XOR);
>
> //Setup the CLC1 inputs
> clc1_setup_input(1, CLC_INPUT_CLCIN0); //input 1 set to CLCIN0
> clc1_setup_input(2, CLC_INPUT_CLCIN1); //input 2 set to CLCIN1
> clc1_setup_input(3, CLC_INPUT_CLCIN0); //input 3 set to CLCIN0, not
> using this input
> clc1_setup_input(4, CLC_INPUT_CLCIN0); //input 4 set to CLCIN0, not
> using this input
>
> //Setup the CLC1 gates
> clc1_setup_gate(1, CLC_GATE_NON_INVERTED_INPUT_1); //set gate 1 to
> non inverting input 1
> clc1_setup_gate(2, CLC_GATE_CLEAR); //set gate 2 to always
> output 0
> clc1_setup_gate(3, CLC_GATE_NON_INVERTED_INPUT_2); //set gate 3 to
> non inverting input 2
> clc1_setup_gate(4, CLC_GATE_CLEAR); //set gate 4 to always
> output 0
>
> The setups for CLC2, CLC3 and CLC4 would be similar, just change the
> calls to the functions to setup_clc2(), clc2_setup_input() and
> clc2_setup_gate() for CLC2, setup_clc3(), clc3_setup_input() and
> clc3_setup_gate() for CLC3, and setup_clc4(), clc4_setup_input() and
> clc4_setup_gate() for CLC4. The built-in functions will automatically
> set the CLCSELECT register based on which CLC you're setting up.
>
> If you want to manually setup the CLC peripherals then you'll need to
> set the CLCSELECT register to the one you want to setup, before
> writing the CLCnCON, CLCnGLS0, CLCnGLS1, CLCnGLS2, CLCnGLS3, CLCnPOL,
> CLCnSEL0, CLCnSEL1, CLCnSEL2 and CLCnSEL3 registers. Write 0 to the
> CLCSELECT register to setup CLC1, write 1 to the CLCSELECT register to
> setup CLC2, write 2 to the CLCSELECT register to setup CLC3 and write
> 3 to the CLCSELECT register to setup CLC4.
>
> Richard
> CCS Support |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19538
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| Posted: Wed Oct 23, 2024 7:46 am |
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Ah,
So there isn't actually a CLC2CON register. There is a single CLCnCON
register, which talks to CLC1, 2, 3 etc., according to char is in CLCSELECT.
That needs careful reading of the data sheet to see..... |
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