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Woody
Joined: 11 Sep 2003
Posts: 83
Location: Warmenhuizen - NL
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| Learned something about Timer0, at least on an 18F55Q43 |
 Posted: Wed Nov 02, 2022 4:19 am |
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I use Timer0 as the go-to timer in nearly all of my programs. Its interrupt is used to maintain timers to blink leds, generate seconds or minutes, pulse relays, debounce switches and what not. Normally it interrupts every 1ms.
I set up timer0 to match the system clock in a way that I can use an 8 bit value in set_timer0() to program the T0 counter to generate an overflow every 1 ms. So for instance for a 16MHz system clock I would use:
| Code: |
#define T0_CAL 132
setup_timer_0(T0_INTERNAL | T0_8_BIT | T0_DIV_32);
set_timer0(T0_CAL);
enable_interrupts(INT_TIMER0);
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Then in the timer isr first thing I do is reset the T0 counter.
| Code: |
#INT_TIMER0
void clock_isr(void) {
set_timer0(T0_CAL);
// Do everything else
}
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This gives me a 1kHz +- a couple of Hz interrupt frequency. I picked this up somewhere over here and used it for as long as I can remember.
Reading the DS for my favorite PIC this morning I found an alternative way of doing this. It seems when I use T0 in 8bit mode (check) I can set TMR0H to a value, T0 then counts to this value, resets to 0, copies TMR0H to a buffer and does it again.
| Code: |
#define TMR0H_VAL 124
#byte T0H = getenv("SFR:TMR0H")
setup_timer_0(T0_INTERNAL | T0_8_BIT | T0_DIV_32);
T0H=TMR0H_VAL;
enable_interrupts(INT_TIMER0);
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| Code: |
#INT_TIMER0
void clock_isr(void) {
// Do nothing with T0 :-)
// Do everything else
}
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I implemented that and hey: three instructions less in setting up, six instructions less in the isr and a slightly more precise timer interrupt! 
Probably no news to many, but new to me and maybe of use to some. |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19539
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| Posted: Wed Nov 02, 2022 9:14 am |
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This is only available on relatively 'recent' chips.
Historically only timer2 supported a programmable period.
Critical line in the data sheet for this timer:
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8-bit timer with programmable period
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Been available on many chips in the last few years, but not before that.
I just did a search through some of the datasheets, and a couple of chips
that launched in 2017 do not offer this. None before that I have found
give this. A couple that came in 2018 have it. So the XXK40 chips, your
Q43, the 66K80 etc.
So if looking at chips that have launched in the last four years, look for
this. |
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DaveS
Joined: 05 Feb 2024
Posts: 1
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| Posted: Mon Feb 05, 2024 1:38 pm |
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I just wanted to remind people to check for updated chip errata from Microchip when using TIMER0. This timer is unlike timers1..6 and is older design. On some pics it also has errata with interrupt priority bits.
I used a pic18F26K40 and in June 2022 they added a new errata for TIMER0 which just bit me on newer CPUS. They worked for years, but now
some cpus timer0 won't work unless you init in ASYNCHRONOUS mode!!!
On CCS this means adding T0_INPUT_NOT_SYNCHRONIZED flag as the work-around.
// example of async work around for errata
setup_timer_0(T0_INTERNAL|T0_INPUT_NOT_SYNCRONIZED|T0_DIV_64|T0_8_BIT, 250, 1); |
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